The present invention relates to the field of semiconductor devices, computer systems, their manufacture, and operation. More specifically, in one embodiment the invention provides an improved technique for direct memory access (DMA) transfers in a computer system, as well as an apparatus for performing DMA transfers.
In computer systems, data are transferred over one or more buses in the system. In some computer systems, data transfers always are made via a central microprocessor or central processing unit (CPU). In such computer systems a transfer of data from, for example, a disk drive to memory requires intervention of the central processing unit. This frequently causes the overall operation of the computer system to slow substantially because the CPU spends substantial amounts of time involved in such data transfers between peripheral devices rather than conducting the core operations of the computer system.
In order to overcome this difficulty, a variety of solutions have been proposed. One such solution is the use of a direct memory access (DMA) controller. FIG. 1 is an overall block diagram illustrating a computer system 2 which utilizes a DMA controller 4. The system includes well known buses such as a data bus 6, address bus 8, and control bus 10. Central operations in the system are conducted on a microprocessor 12 and utilize data in memory 14. Output from the system is made via one or more output ports, host adapters, or other devices 16 and input to the system is made via one or more input devices 18.
The DMA controller is a specialized purpose processor which moves data according to a desired program. The DMA controller enables the transfer of data from or to, for example, an input port such as a disk drive to memory without the use of the microprocessor. DMA controllers result in faster transfer of large blocks of data within the system and are commonly used as, for example, disk interfaces, local network interfaces, video interfaces, and the like. Often several DMA devices will be included in a system wherein a single DMA chip will service a single peripheral device or group of devices. DMA devices and their operation are described in, for example, Kraft et al., Mini/Microcomputer Hardware Design, Chapter 9 (1979) and Wakerly, Microcomputer Architecture and Programming, Chapter 11 (1989), which are incorporated herein by reference for all purposes.
In a conventional DMA transfer (using a SCSI port as an example of DMA applications) a DMA controller is intialized by setting a memory address, SCSI port address, and block length registers. The DMA controller then waits for the SCSI controller to indicate it is ready for data. The DMA controller then blocks access of the CPU to the bus, reads a block of data directly from memory, and writes it to the SCSI controller. The DMA controller then allows the CPU to continue operating until the SCSI controller is ready for another block of data. Such operations result in substantial speed increases particularly when used in conjunction with specialized software. DMA controllers currently include the Intel 82380 and AMD Am9517A/8237A devices.
While meeting with substantial success, prior DMA controllers have also met with certain limitations. For example, many prior DMA controllers utilize a word count register and increment the register by 1 each time a data transfer takes place. When the last word has been transferred a carry is generated which indicates that the transfer operation has been completed. Other systems store the final address of a buffer in an end address register. After each data transfer, a current address register is compared to the final address. If the values are equal the transfer is complete; if the values are not equal the current address register is incremented and processing continues. With either of the above systems, the DMA controller operates somewhat inefficiently when data are, for example, contained in non-contiguous blocks on a hard disk or disk drive. This occurs because the counters must be reset each time a new sector or data block is accessed on, for example, a hard disk. This is of particular concern when, for example, a disk is disconnected in the middle of a read operation. The data being read are contained on separate tracks, the counter in prior DMA systems must be reset entirely, and the disk drive must perform another seek operation and recover all of the data in question. Since seek operations are exceedingly slow, this can substantially slow system operation. Of course, disk drive applications are only exemplary of systems with this limitation. A wide variety of additional applications (such as networks) also suffer from this limitation.
From the above it is seen that an improved DMA controller and method of operation therefor are needed.